HPK taruh disini
- RISC processors have a fixed instruction size. CISC microcontroller such as the 8051, instructions can be 1, 2, or even 3 bytes. Therefore, the CPU can decode the instructions quickly.
- RISC architecture is a large number of registers. It have at least 32 registers. One advantage of a large number of registers is that it avoids the need for a large stack to store parameters.
- RISC processors have only instructions such as ADD, SUB, MUL, LOAD, STORE, AND, OR, EOR, CALL, JUMP, and so on.
- RISC is used more commonly in high-level language environments such as the C programming language rather than Assembly language environtments.
- The most important characteristic of the RISC processor is that more than 95% of instructions are executed with only one clock cycle, in contrast to CISC instructions. Code scheduling is most often the job of the compiler.
- RISC processors have separate buses for data and code. In all the x86 processors, there is one set of buses for the address and another set of buses for data carrying opcodes and operands in and out of the CPU. RISC processors, there are four set of buses:
- a set of data buses for carrying data (operand) in and out of the CPU,
- A set of address buses for accessing the data,
- A set of buses to carry the opcodes,
- A set of address buses to access the opcodes.
- Because CISC has such a large number of instructions, each with so many different addressing modes, microinstructions (microcode) are used to implement them.
- The implementations of microinstructions inside the CPU employs more than 40-60% of transistors in many CISC processors.
- Hardwiring of RISC instructions takes no more than 10% of the transistors.
